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?common address inputs and data inputs / outputs for sram and otp description features ?65,536-word x 16-bit / 131,072-word x 8-bit configuration sram and 1,048,576-word x 16-bit / 2,097,152-word x 8-bit configuration otp ?power supply voltage : 2.7 to 3.6v ?fully static operation ?operating temperature range : ta= -20 to 70 c ?3-state output ?data retention available at power supply voltage 1.5v for sram ?package options : 48-pin plastic tsop (type ii) (tsop48-p-550-0.8) (product : MS52C1162Ata) 48-pin plastic fbga (fbga48-p-0913-0.8) (product : MS52C1162Ala) ?access time : 100ns max (vcc=2.7v) 80ns max (vcc=3.0v) semiconductor MS52C1162A the MS52C1162A is a 65,536 -word by 16 -bit / 131,072-word by 8-bit electrically switchable 1mb static ram and 1,048,576-word by 16-bit / 2,097,152-word by 8-bit electrically switchable 16mb one time prom featuring 2.7v to 3.6v power supply operation and direct lvttl input / output compatibility. since the circuitry is completely static,external clocks are unnecessary, making this device very easy to use. the MS52C1162A is packaged in 48-pin plastic tsop and 48-pin fbga (9mmx13mm) ,suited for use in handy terminal and other application which required small space. preliminary 1998.6 ?input / output lvttl compatible 1 65,536-word x 16-bit or 131,072-word x 8-bit static ram + 1,048,576-word x 16-bit or 2,097,152-word x 8-bit one time prom ?
MS52C1162A pin configuration (top view) a1 a2 i/o1 a3 a4 a5 vcc gnd vcc i/o13 i/o14 a13 a12 a11 a17 a15 a14 oe ceo 48-pin tsop (ii) i/o15/a-1 i/o2 gnd 2 i/o4 a10 a6 i/o8 i/o9 i/o0 i/o3 a18 i/o11 i/o10 i/o12 i/o5 i/o6 i/o7 a16 ces a9 we a8 a0 a7 byte/vpp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 23 24 45 46 47 48 nc a19 nc nc
MS52C1162A pin configuration (top view) a1 a2 i/o1 a3 a4 a5 vcc gnd nc vcc i/o13 i/o14 a13 a12 a11 a17 a15 a14 pin name function a -1 - a15 a16 - a19 ceo we oe i/o0 - i/o15 vcc byte/vpp gnd nc common address inputs address inputs for otp chip enable for sram chip enable for otp write enable for sram common output enable common data inputs / outputs common power supply common mode switch & common ground no connection oe ceo 48-pin fbga 6 a 5 4 3 2 1 bcdefgh i/o15/a-1 i/o2 gnd 3 i/o4 a10 a6 i/o8 i/o9 i/o0 i/o3 nc a18 i/o11 i/o10 i/o12 i/o5 i/o6 i/o7 a16 ces a9 we a8 nc a0 a7 ces a19 program power supply for otp byte/vpp
MS52C1162A block diagram function table standby sram read sram write operating mode ceo ces we oe byte / vpp vcc i/o0 - i/o7 2.7v to 3.6v h h h h h l h h h l l l * h h * * * * h l h h l high-z high-z d in d out * * * note : 1. * = don't care ("h" or "l") 2. it is forbidden to apply ceo="l" and ces="l" simultaneously. a-1 a0 a1 a16 a17 a18 a19 ceo ces byte we oe i/o0 i/o1 i/o2 i/o3 i/o12 i/o13 i/o14 i/o15 vcc vpp gnd sram memory array 64kw x 16b or 128kw x 8b otp memory array 1mw x 16b or 2mw x 8b output buffer address buffer control . . . . . . . . . . . . . . . . row decoder column decoder row decoder column decoder multiplexer multiplexer a2 4 . . . . . . . . . . . . i/o8 - i/o14 i/o15 / a-1 h h l * high-z high-z high-z high-z 16-bit 8-bit hl 16-bit 8-bit h h h l l l h h hl hl l l * * l h high-z high-z d out d out d in high-z high-z d out high-z l / h d in d in high-z l / h * 16-bit 8-bit otp read l l l h h l l l h h d out d out d out high-z high-z high-z d out high-z high-z * l / h high-z
MS52C1162A absolute maximum ratings rating v w c 0.7 operating temperature electrical characteristics unit condition symbol parameter power supply voltage output voltage power dissipation storage temperature v o p d t opr t stg ta=25 c respect to gnd -0.5 to 5.0 -0.5* to vcc+0.5 -20 to 70 -55 to 125 v c * -1.2vmin. for pulse width less than 30ns. recommended operating conditions v input high voltage unit condition symbol parameter power supply voltage sram v cc v input low voltage v cch v ih v il min. max. typ. 2.7 3.6 000 1.5 3.6 2.2 -0.5* 0.4 v v v vcc=2.7 to 3.6 input voltage v i v v -0.5 to 11.5 -0.5* to vcc+0.5 gnd v pp v -0.5 vcc+0.5 (ta= -20 to 70 c ) 5 v cc v pp function table (continued) otp program operating mode ceo ces we oe byte / vpp vcc i/o0 - i/o7 4.0v l h h h * i/o8 - i/o14 i/o15 / a-1 h high-z high-z 9.75v otp program inhibit otp program verify h h h l high-z d in d in d in d out d out d out * * vcc+0.5 note : 1. * = don't care ("h" or "l") 2. it is forbidden to apply ceo="l" and ces="l" simultaneously. * -1.2vmin. for pulse width less than 30ns. data retention voltage
MS52C1162A dc characteristics (1) (vcc=3.0v 0.3v,ta=-20 to 70 c) parameter symbol unit min. max. input leakage current output leakage current m a i li condition output high voltage output low voltage standby power supply current operating power supply current v oh v ol i cca i ccs typ. 1.0 0.4 vcc-0.5 v v i oh = - 500 m a i ol =2.1ma ce o =v ih , ce s =v ih or i lo we=v il v out =0 to v cc v in =0 to v cc -1.0 1.0 -1.0 m a ce o 3 v cc- 0.2v v in =0 to v cc ce s 3 v cc- 0.2v i ccs1 ce o =v ih (sram) i cca * (otp) 10 0.3 m a ma ce o =v ih v in =v ih /v il t cyc =100ns ce o 3 v cc- 0.2v t cyc =1 m s ce s 0.2v v il 0.2v v ih 3 v cc- 0.2v ceo=v il v in =v ih /v il t cyc =100ns oe=v ih v pp power supply current i pp byte/v pp =v cc 35 ma 10 ma 35 ma 10 oe=v ih oe 3 v cc- 0.2v m a * read current oe=v ih or 6 ces=v ih ce s =v il ce s =v ih v in =v ih or v il ce o 0.2v t cyc =1 m s ce s 3 v cc- 0.2v v il 0.2v v ih 3 v cc- 0.2v oe 3 v cc- 0.2v 20 ma
MS52C1162A dc characteristics (2) (vcc=3.3v 0.3v,ta=-20 to 70 c) parameter symbol unit min. max. input leakage current output leakage current m a i li condition output high voltage output low voltage standby power supply current operating power supply current v oh v ol i cca i ccs typ. 1.0 0.4 vcc-0.5 v v i oh = - 500 m a i ol =2.1ma ce o =v ih , ce s =v ih or i lo we=v il v out =0 to v cc v in =0 to v cc -1.0 1.0 -1.0 m a ce o 3 v cc- 0.2v v in =0 to v cc ce s 3 v cc- 0.2v i ccs1 ce o =v ih (sram) i cca * (otp) 10 0.3 m a ma ce o =v ih v in =v ih /v il t cyc =80ns ce o 3 v cc- 0.2v t cyc =1 m s ce s 0.2v v il 0.2v v ih 3 v cc- 0.2v ceo=v il v in =v ih /v il t cyc =80ns oe=v ih v pp power supply current i pp byte/v pp =v cc 40 ma 15 ma 40 ma 10 oe=v ih oe 3 v cc- 0.2v m a * read current oe=v ih or 7 ces=v ih ce s =v il ce s =v ih v in =v ih or v il ce o 0.2v t cyc =1 m s ce s 3 v cc- 0.2v v il 0.2v v ih 3 v cc- 0.2v oe 3 v cc- 0.2v 25 ma
MS52C1162A sram ac characteristics 8 sram read cycle (1) parameter symbol unit min. max. read cycle time address access time ces access time oe access time ces to output in low-z oe to output in low-z output hold from address change ces to output in high-z oe to output in high-z ns ns ns ns ns ns ns t rc t aa t oe t olz t oh t ohz 100 100 100 50 10 5 10 35 35 condition sram write cycle (1) write cycle time address setup time data setup time ces to end of write we to output in high-z ns ns ns ns ns ns t wc t as t ds 100 0 75 0 40 0 write pulse width write recovery time data hold time address valid to end of write output active from end of write ns ns ns t wp t wr t dh t whz t aw t wlz 35 90 90 5 test condition input pulse levels ------------------------- 0.4v/2.4v input timing reference levels --------- 0.8v/2.0v output load --------------------------------- 50pf output timing reference levels ------- 0.8v/2.0v input rise and fall time ----------------- 5ns dout 1.85v 690 50pf (including scope and jig capacitance) ns ns t chz t clz t co ns t cw unit min. max. parameter symbol condition (vcc=3.0v 0.3v,ta=-20 to 70 c) (vcc=3.0v 0.3v,ta=-20 to 70 c)
MS52C1162A 9 sram read cycle (2) parameter symbol unit min. max. read cycle time address access time ces access time oe access time ces to output in low-z oe to output in low-z output hold from address change ces to output in high-z oe to output in high-z ns ns ns ns ns ns ns t rc t aa t oe t olz t oh t ohz 80 80 80 40 10 5 10 30 30 condition sram write cycle (2) write cycle time address setup time data setup time ces to end of write we to output in high-z ns ns ns ns ns ns t wc t as t ds 80 0 60 0 35 0 write pulse width write recovery time data hold time address valid to end of write output active from end of write ns ns ns t wp t wr t dh t whz t aw t wlz 30 70 70 5 test condition input pulse levels ------------------------- 0.4v/2.4v input timing reference levels --------- 0.8v/2.0v output load --------------------------------- 50pf output timing reference levels ------- 0.8v/2.0v input rise and fall time ----------------- 5ns dout 1.85v 690 50pf (including scope and jig capacitance) ns ns t chz t clz t co ns t cw unit min. max. parameter symbol condition (vcc=3.3v 0.3v,ta=-20 to 70 c) (vcc=3.3v 0.3v,ta=-20 to 70 c)
8-bit read mode (byte=v il ) sram read cycle (2) MS52C1162A a0 - a15 t rc ces t aa t co t clz t olz t oh t chz sram timing diagrams oe t oe t ohz valid data-out i/o0 - i/o15 10 16-bit read mode (byte=v ih ) sram read cycle (1) a-1 - a15 t rc ces t aa t co t clz t olz t oh t chz oe t oe t ohz valid data-out i/o0 - i/o7 i/o8 - i/o15 high-z high-z notes : 1. a read cycle of sram occurs during the overlap of ceo="h", ces="l", oe="l" and we="h". 2. t ohz , t chz are specified by the time when data is floating , not defined by the output level.
8-bit write mode (byte=v il ) sram write cycle (2) 16-bit write mode (byte=v ih ) sram write cycle (1) MS52C1162A t wc t wp t whz t wlz data-in t cw t aw t as t wr t ds t dh a0 - a15 ces we din dout 11 (i/o0 - i/o15) t wc t wp t whz t wlz data-in t cw t aw t as t wr t ds t dh a-1 - a15 ces we din dout (i/o0 - i/o7) i/o8 - i/o15 high-z high-z
2. oe may be either of "h" or "l" in the write cycle of sram. 3. t as is specified from ces="l" or we="l" , whichever occurs last. 4. t wp is an overlap time of ces="l" and we="l". 5. t wr , t ds , t dh are specified from ces="h" or we="h" , whichever occurs first. 6. t whz is specified by the time when data output is floating , not defined by the output level. MS52C1162A sram data retention characteristics parameter symbol condition min. typ. max. unit (ta=-20 to 70 c) v cc 2.7v v ih v cch ces 0v ces 3 v cc- 0.2v t cdr t r data retention mode ceo 3 v cc- 0.2v ces 3 v cc- 0.2v v in =0 to v cc v cc =1.5v ceo 3 v cc- 0.2v ces 3 v cc- 0.2v v in =0 to v cc 1.5 3 v m a ns ms 0 5 v cch i cch t cdr t r data retention power supply voltage data retention power supply current operation recovery time chip deselect to data retention time notes : 1. a write cycle of sram occurs during the overlap of ceo="h" , ces="l" and we="l". 12 7. when i/o pins are in the output mode , don't apply the inverted input signal to the output pins.
test condition dout 1.85v 690 50pf MS52C1162A otp ac characteristics (1) parameter symbol unit min. max. read cycle time address access time ns ns ns ns ns t rc 0 condition ceo access time oe access time ns ns t co t oe output hold t ohz t chz t oh 100 100 100 50 40 35 0 0 ce o =oe=v il oe=v il ce o =v il oe=v il ce o =v il ce o =oe=v il otp read cycle (2) otp read cycle (1) 13 t aa ceo to output in high-z oe to output in high-z parameter symbol unit min. max. read cycle time address access time ns ns ns ns ns t rc 0 condition ceo access time oe access time ns ns t co t oe t ohz t chz t oh 80 80 80 50 40 35 0 0 ce o =oe=v il oe=v il ce o =v il oe=v il ce o =v il ce o =oe=v il t aa ceo to output in high-z oe to output in high-z (vcc=3.0v 0.3v,ta=-20 to 70 c) (vcc=3.3v 0.3v,ta=-20 to 70 c) from address change output hold from address change input pulse levels ------------------------- 0.4v/2.4v input timing reference levels --------- 0.8v/2.0v output load --------------------------------- 50pf output timing reference levels ------- 0.8v/2.0v input rise and fall time ----------------- 5ns (including scope and jig capacitance)
notes : 1. a read cycle of otp occurs during the overlap of ceo="l", ces="h" and oe="l". 2. t ohz , t chz are specified by the time when data is floating , not defined by the output level. 16-bit read mode (byte=v ih ) otp read cycle (1) 8-bit read mode (byte=v il ) otp read cycle (2) MS52C1162A 14 a0 - a19 t rc ceo t aa t co t oh t chz otp timing diagrams oe t oe t ohz valid data-out i/o0 - i/o15 a-1 - a19 t rc ceo t aa t co t oh t chz oe t oe t ohz valid data-out i/o0 - i/o7 i/o8 - i/o15 high-z high-z
MS52C1162A 15 otp dc characteristics (ta=25 c 5 c) parameter symbol unit min. max. input leakage current program power supply current m a i li condition power supply current input high voltage v input low voltage output high voltage output low voltage program voltage v cc voltage i pp2 i cc v ih v ih v oh v ol v cc v pp typ. 10 50 50 v cc +0.5 0.8 0.45 4.1 9.75 4.0 9.5 3.9 3.0 -0.5 2.4 ma ma v v v v v i oh=-500 m a i ol=2.1ma ce o =v il v i= v cc+0.5v 10.0 otp programming operation (vcc=4.0v 0.1v,v pp =9.75v 0.25v,ta=25 c 5 c) otp ac characteristics (2) address setup time oe setup time data setup time address hold time oe to output in high-z v pp power setup time t as t oes t ds t ah t dh t dfp t vs t pw ns m s program pulse width 10 11 9 130 2 2 2 0 2 0 2 data valid from oe t oe ns 150 data hold time m s m s m s m s m s m s otp programming operation parameter symbol unit min. max. condition typ. pin check function pin check function is to check contact between each device-pin and each socket-lead with eprom programmer. setting up address as the following condition call the preprogrammed codes on device outputs. a0 (v cc =3.3v 0.3v,ceo=v il ,byte/v pp =v ih ,ta=25 c 5 c) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 01 0 10 1 01 0 vh* 0 1 01 0 10 0 11 1 0 1 0 1 0 1 0 1 vh* 1 01 0 10 1 10 0 data ff00 00ff * :vh=8v
otp programming waveform d out t pw t oes t ah a0 - a19 ce o i/o0 - i/o15 t dfp note : when otp is programming mode , ces should be "h" level. t as t ce program verify d in program t dh t ds t vs oe byte/vpp 16 MS52C1162A capacitance unit condition symbol parameter input capacitance c in1 min. max. typ. 10 60 pf pf c in2 v i =0v (vcc=3.3v , ta=25 c , f=1mhz) c i/o input/output capacitance note : this parameter is periodically sampled and not 100% tested. v o =0v 10 pf byte/v pp capacitance
program 10 m s increment address increment address bad insertion bad insertion MS52C1162A otp programming / verify flow chart 17 v cc =4.0v v pp =9.75v x=0 yes pass no ng no yes ng pass x=5? x=x+1 yes no v cc =3.0v v pp =3.0v programming pin check no ok v cc =3.6v v pp =3.6v ng pass v cc =3.0v v pp =3.0v ng pass verify no ok start start pin check last address ? address = first location program 10 m s verify (one byte) last address ? verify (one byte) device passed device failed device passed device failed verify (one byte) verify (one byte) address = first location address = first location
semiconductor notice the information contained herein can change without notice owing to product and/or technical im- provements. before using the product, please make sure that the information being referred to is up-to- date. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected opera- tion resulting from misuse, neglect, improper installation, repair, alteration or accident, improper han- dling, or unusual physical or electrical stress including, but not limited to, exposure to parameters be- yond the specified maximum ratings or operation outside the specified operating range. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. the products listed in this document are intended for use in general electronics equipment for commer- cial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety de- vices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. certain products in this document may need government approval before they can be exported to par- ticular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. all brand, company and product names are the trademarks or registered trademarks of their respective owners. copyright 1998 oki electric industry co., ltd.
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